Poster

R2G：A Multi-View Circuit Graph Benchmark Suite from RTL to GDSII

ZEWEI ZHOU ⋅ Jiajun Zou ⋅ Jiajia Zhang ⋅ Ao Yang ⋅ Ruichao He ⋅ Haozheng Zhou ⋅ Ao Liu ⋅ Jiawei Liu ⋅ Leilei Jin ⋅ Shan Shen ⋅ Daying Sun

Abstract

Progress in machine learning for electronic design automation (EDA) is constrained by the lack of open, multi-view graph datasets that coherently represent the same circuits across late physical-design stages. We present R2G (RTL-to-GDSII), a standardized benchmark and framework that converts DEF files into typed, heterogeneous, information-preserving circuit graphs and supports node- and edge-level tasks in placement and routing. R2G provides five stage-aware views with information parity and includes loaders, unified splits, domain-specific metrics, and reproducible baselines—enabling fair cross-view comparison and isolating representation from modeling. In systematic studies with classic GNNs (GIN, GAT, GatedGCN), we show that view choice strongly affects performance, varies with stage and supervision, and that decoder-head depth (3--4 layers) improves accuracy and stability; these findings connect view semantics to objectives and message passing and offer practical guidance. By bridging EDA semantics and graph learning, R2G releases large-scale datasets and an end-to-end pipeline, creating an open testbed for principled representation design. Datasets, loaders, and evaluation scripts will be released on GitHub.